Digital reference source



April 16, 1968 5. 3,378,692

DIG ITAL REFERENCE SOURCE Filed Sept. 8. 1964 5 Sheets-Sheet 1 REFERENCE g gg BAND--PASS \3 K I AMPLIFIER 7 I I C I 2 CLOCK SIGNAL 7 I Tw PHAsE }LOGICAL CARRIER REFERENCE GENERATOR 2 QUADRATURE SINUSOIDAL BAND-PASS e, CARRIER CLOCK- I I c PULSE FIOI' I I I I I I I I t GENERATOR CLOCK F I d PULSE I02 om,

SWITCH cLocI V4 SIGNAL FI II GIOZ 0 V4 1 FIG.3

INVENTOR. CHARLES E. LENZ ATTORNEY April 16, 1968 c. E. LENZ 3,378,692

DIGITAL REFERENCE SOURCE Filed Sept. 8, 1964 5 Sheets-Sheet 5 CLOCK c1 TJHI IILLIIIJIIM F l i l k F202 cm I I CARRIER- l COUNTER F203 111 STATE 0L Ll k F os fi L L OUTPUT o p q TRIGGER aol w l i l REFERENCE CARRIER 206 o w GENERATOR x ,W OUTPUT E07 0 1r 2 1 25 f t 206 0 SINUSOIDAL REFERENCE e FIG.4

INVENTOR. CHARLES E. LENZ ATTORNEY United States Patent 3,378,692 DIGITAL REFERENCE SOURCE Charles E. Lenz, Fullerton, Califi, assignor to North American Rockwell Corporation, a corporation of Delaware Filed Sept. 8, 1964, Ser. No. 394,977 7 Claims. (Cl. 307-106) ABSTRACT OF THE DISCLOSURE A digital reference source providing a pair of square Waves of equal period and controlled 90 phase relationship. A master oscillator produces a train of pulses at regularly spaced intervals. A counter counts the pulses and produces an output when a predetermined count has been reached. The counter output is ANDed wit-h pulses from This invention relates to a waveform generator and more specifically to a generator for accurately producing square waves having both accurately controlled phase and frequency.

In digital systems and more specifically in digital servo control systems, square Waves are employed for various functions. Many conventional square wave generators are unsatisfactory in high accuracy digital control systems due to the inaccurate or uncertain time occurence of the leading and trailing edges of these square waves. Hence, the accuracy of the entire digital servo system could be determined by such a square wave generator.

Accordingly, an object of the invention is to provide a new and improved square wave generator.

Another object of this invention is to provide logical square waves, directly from flip-flops of the'reference source without intervening gates.

Still another object of this invention is to provide a means for assuring minimum delay in triggering a twophase square wave reference source from a primary clock source.

Yet still another object of this invention is to provide a square wave reference source which does not utilize monostable logic elements.

A further object of the invention is a provision of a generator for accurately producing two square wave outputs.

A still further object of the invention is to provide a generator for producing square waves having accurately controlled leading and trailing edges with the effective noise and other outside factors being at a minimum.

A yet still further object of this invention is to provide a square wave generator for producing square waves having an accurately controlled phase relationship with respect to each other.

In order to accomplish the above objects, the present invention utilizes a high speed counter to count clock pulses from a source of clock pulses. When a true count of a predetermined number of pulses is achieved, a signal from the counter will be emitted to a gating circuit. When the predetermined relationship between this signal and another clock pulse occurs in the gating circuit, a triggering signal will be generated which will determine the time of the leading or trailing edge of the generated square waves, In so utilizing this counter, a square wave signal is accurately and precisely generated.

Further, the reference source incorporates a number of features which contribute to the simplicity, reliability, and accuracy of the digital control or other system with which it is associated. The clock period is controlled by a master crystal oscillator in such a manner that clock-pulse shaped and duration are independent of changes in oscillator waveform. A simple two-phase reference-carrier generator produces'sine and cosine carriers without gating irregularities which cause analog waveform distortion and resultant control-system inaccuracy. Zero crossings of the reference carriers are automatically synchronized with the clock signals, reducing by one-half the uncertainty of measuring phase by asynchronous digital means. Proper sineand cosine-carrier phasing is automatic, eliminating carrier-generator presetting either after power application or after a severe noise disturbance. Monostable elements have eliminated for noise immunity.

The previously mentioned objects and additional objects of the invention may be better understood by reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of the digital reference source;

FIG. 2 is a logic diagram of the two-phase clock and the two-phase reference-carrier generator;

FIG. 3 illustrates the waveforms present throughout the two-phase clock.

FIG. 4 illustrates the waveforms present through the two-phase reference-carrier generator.

The digital reference source can supply all reference signals required by a digital position-control system of the phase-comparison type; moreover, the components used can be employed together or individually to supply reference signals for a variety of other types of digital systems. The specific nature of the reference signals generated and the means used to generate them have evolved from laboratory experience with less satisfactory approaches which ultimately led to the accurate and reliable components and methods to be described. The design of the reference source has led to both improvement in performance and reduction in complexity of digital systems with which it has been used.

The block diagram of the digital reference source in FIG. 1 shows the two-phase clock 1 which furnishes the time base for the digital reference source. The clock 1 is synchronized by a crystal master oscillator 5, and illustrated in 'FIG. 2, which produces either a sinusoidal output of frequency w or an arbitrary periodic output of the same fundamental frequency. The two-phase clock 1 produces two normally false output signals, C and C illustrated in FIG. 3e and f, each of duty cycle 0.25 and T=81r/w If the time scale is selected so that a pulse of the primary clock train C terminates at 1, then the first pulse of the second clock train C for t 0 will terminature at t=1-/ 2. The clock signals C and C are both directed to the associated digital control or other system;

C is also directed to the tWo-phase reference-carrier generator 2, as shown in FIG. 1. For a period 7/4 after a pulse of either clock signal, C C =0; this time period is provided to permit the settling of flip-flops either for interrogation after triggering or for triggering after override presetting. Although the two clock signals can be used in various ways in an associated digital system, C is normally employed for triggering flip-flops, while C is used both for interrogation to determine the states of flipfiops after settling and for override resetting of flip-flops.

As shown in FIG. 1, the only input to the two-phase reference-carrier generator 2 is the clock signal C Synchronized by this clock signal, the reference-carrier generator 2 produces two balanced square-wave carrier outputs, the logical reference carrier X and the logical quadrature carrier X Both X and X are of period 171 7, where the positive integer m is divisible by 4 and is a design parameter of the reference-carrier generator 2. The signals X and X shown in FIG. 4, go through all logical transitions in synchronism with the trailing edges of C pulses. If the time scale is selected so that X goes true (i.e., from to l) at t=0, then X, will have a 0-to-1 transition whenever.

where p is any non-negative integer, and will have a 1-to-0 transition whenever Using the same time scale, X (0)=1 and X will have a 1-to-0 transition whenever t=(4p+1)m 'r/4 (3) and will have a 0-to-1 transition whenever t: (4p+3)m r/4 If X and X are passed through identical reference and quadrature band-pass amplifiers, 3 and 4 respectively, tuned to ca as shown in FIG. 1, then the respective output signals will be e,=k sin w t (5) and e =k cos w (6) where for unity-gain amplifiers and unity peak-to-peak amplitude amplifier inputs. In this manner, two-phase sinusoidal signals are produced for use, for example, as inputs for a resolver-type output transducer of an associated digital control system connected to produce a constant-amplitude output with phase relative to the electrical angle of e,- proportional to the shaft angle. If the reference and quadrature band-pass amplifiers, 3 and 4 respectively, in FIG. 1 are identical, the phase between e and e is not dependent upon either the clock period 'T or the frequency w of the master oscillator 5 from which it is derived. In practice, this characteristic permits minor changes in oscillator frequency to be tolerated without phase error. The logical carrier signals X and X can also be used directly as inputs for the logical section of an associated digital control or other system.

Normally no preset signals need be applied to the digital reference source, as the state of the source itself provides the reference for all measurements and presetting of states in the associated digital control or other system.

Operation of components A logic diagram showing the unique components of the digital reference source appears in FIG. 2. The signals which are inputs to and outputs from the various components correspond to those shown in FIG. 1. The reference and quadrature band-pass amplifiers, 3 and 4 respectively, shown in FIG. 1 are of conventional design and do not appear in FIG. 2. (Ref. to Lloyd P. Hunter, Handbook of Semiconductor Electronics, pp. 12-14 thru 12-26; Arthur W. Lo et al., Transistor Electronics, pp. 310-335; and RCA Transistor Manual, pp. 29-33.)

Trailing-edge triggering whereby each flip-flop is responsive only to l-to-O transitions at its trigger input is assumed throughout FIG. 2. All flip-flops are of the clocked IK type. (Ref. to Montgomery Phister, In, Logical Design of Digital Computers, pp. 128-129, 134- 135.) Symbols associated with the inputs and outputs of a typical flip-flop are defined as follows, wherein the a subscript a designates the specific flip-flop (e.g., a=101 refers to flip-flop P in FIG. 2):

1 =set-enable (1) input of flip-flop F T =clock or trig er (T) input of flip-flop F 0 =reset-enable (K) input of flip-flop F F =normal output of flip-flop F F =complement output of flip-fiop F The logic diagram of the two-phase clock 1 is illustrated in FIG. 2. Corresponding waveforms are shown in FIG. 3. In FIG. 3a, the sinusoidal wave e is generated by the master oscillator S, normally a crystal oscillator of conventional design (Ref. to Lloyd P. Hunter, op. cit., pp. 14-18 and 14-19; Arthur W. Lo et al., op. cit., pp. 366-377, 382-383; and RCA Transistor Manual, pp. 39-40) at an angular frequency w The two-phase clock 1 functions by first producing a clock train of duty cycle 0.5 with a waveform independent of the waveform at the output of the master oscillator 5 and then directing alternate pulses to the output C and C The master-oscillator output e is converted to a square wave (shown in FIG. 31)) by the trigger T which is connected to produce a false output (T =0) when e ZO and a true output (T l) when e 0. The complement output of T is connected to the trigger input of flip-flop F which is arranged to toggle on each l-to-O transition of i The resultant output is shown in FIG. 30. The signal F is essentially the OR-function C +C It should be noted that the same waveform would be produced at F for a variety of waveforms at c as long as the angular frequency of the fundamental component of e is w This feature makes the waveforms of the outputs of the two-phase clock 1 independent of variations in the waveform of the output of the master oscillator 5 due to aging or environmental changes.

Once the clock-pulse train F has been obtained, the problem of directing alternate pulses to outputs C and C of the two-phase clock 1 remains. This operation is accomplished by the clock-pulse switch P in conjunction with the AND-gates G and G The trigger input of F is connected to the true output of P and F is arranged to toggle in response to each 1-to-0 transition of F The resultant waveform F is shown in FIG. 3d. The true and complement outputs of P are directed to gates G and G respectively, and the clock-pulse train F is also directed to each of these gates. The resultant outputs G shown in FIG. 3e, and G shown in FIG. 3 f, are the required primary and secondary clock signals C and C respectively.

Operation of the two-phase clock 1 is governed by the following logic equations:

F101: 1, (8a) T 101=T Flip-flop F 1 input equations (8b) O i01= 1 (8c) 1 102= I, T 102=Fw Flip-flop F input equations (9b) O 10z= 1, (9c) G101= FIOXFIOZ;

Gate equations io2= 101 102;

O, em O,] (12a) T101: Trigger equations Output equations C2: 0102;

The preceding equations are implemented in the logic diagram shown in FIG. 2

The purpose of the two-phase reference-carrier genera'tor 2, is to produce the logical reference carrier X and the logical quadrature carrier X having, respectively, the fundamental sinusoidal components e,-=k sin ca t and e =k cos w t (16) The signals e and e must be generated in such a man ner that where m is a design parameter of the reference-carrier generator 2 and 1- is the clock period, and in such a mannor that each transition of X and X is in synchronization with a 1-to-0 transition of C The logic diagram of the two-phase reference-carrier generator 2 is shown in FIG. 2. The reference-carrier generator 2 consists essentially of two sections: a highspeed doublet counter composed of flip-flops F thru F and a two-phase output stage composed of flip-flops F and F The gate G triggers the output stage every time the preceding counter assumes a predetermined state.

It is useful to consider the state of the set of flip-flops forming the two-phase reference-carrier generator 2 to represent a binary number or count C,.. This number may be defined as where k k+b 6 (19a) and 5= 2os 2o7+ 2os 207 ,The efliciency of the design of the two-phase referencecarrier generator 2 is demonstrated by the fact that every state of the set of flip-flops used is employed.

Although the counter shown in FIG. 2 consists of two doublets (F -F and Fzog-Fzo4) and an independent flip-flop (F any number of stages can be assembled by employing the same type of counter configuration, using doublets exclusively if an even number of stages is needed or adding a separate flip-flop if an odd number of stages is required. The doublet shown is an efficient logical design since it utilizes no more logic elements than a twostage ripple counter but has only half the delay.

The design parameter m referred to earlier, which may also be considered to be the interpolation ratio for an associated digital control system, is defined by the relationship where j equals the number of flip-flops in the two-phase reference-carrier generator 2, including the two output flip-flops. The parameter m is also the ratio of the reference-carrier period to the clock period. The smallest possible value of j in Relation 20 is 2, corresponding to direct injection of the clock signal C into the trigger inputs of the two output stages. In the example being considered here, i=7, yielding m =128.

The first doublet in FIG. 2, B -F is typical. Flipfiop F is connected to be triggered by each l-to-O transition of its input C while F is connected to be triggered by a 1-to-0 transition of C only when F =1. Thus, F and F together form a two-stage cyclic counter capable of counting from 00 to 11 Since the same trigger input is applied to both flip-flops, there is no ripple delay in response of F to a 1-to-0 transition of C The connection of flip-flops F and F is identical to that of F and F except that the trigger input to both F and F is F instead of C Consequently, F thru F together form a four-stage cyclic counter capable of counting from 0000 to 1111 with only approximately half of the settling delay associated with a ripple counter of the same capacity. Due to the odd number of counter stages required in the base being considered, an independent flip-flop, F is used at the end of the counter. This flip-flop is connected to toggle in response to each l-to-O transition of P The AND-gate G receives an input from the normal output of each of the flip-flops F thru F The clock signal C is an additional input. Consequently, one C pulse is emitted by G each time C,=a a lll11, Where a and a can have the values 0 and 1 in any combination. This gate eliminates the delay between the trailing edge of a C pulse which occurs when C,*=a a 11111 (a a again having any value) and the resultant transition of P from 1 to 0. Although this delay is normally small, it may be of significance When the number of stages in the carrier generator 2 is relatively large and the associated digital control or other system must provide high accuracy. The delay avoided may vary somewhat with environment and component aging.

The output stage of the two-phase reference-carrier generator 2 consists of the two flip-flops F and F Each of these flip-flops receives its trigger input directly from G The logical reference carrier X is the complement output F while the logical quadrature carrier X is complement output F The flip-flops F and F are connected as shown in FIG. 2 so that each supplies the enabling inputs for the other in such a manner that the proper phase relationship always exists be- 'tween the fundamental sinusoidal components of X, and X,,,. The particular logic configuration employed permits each carrier output of the reference-carrier generator 2 to be obtained directly from a flip-flop, thus avoiding the necessity for additional gates and the switching transients sometimes encountered. when intervening gates are employed. Switching transients are particularly undesirable when the analog nature of a logical signal is important, as is the case here. Should the state of either output flip-flop be disturbed by noise, the proper phase relationship between X,. and X will automatically continue; this characteristic also makes presetting of F and F unnecessary when power is applied to the reference-carrier generator 2.

Operation of the two-phase reference-carrier generator 2 is governed by the following logic equations:

1 2o1=1, (21a) T 201=C Flip-flop F input equations (21b) O 2oi=1, (21c) 1 202=F (22a) T zo2=C,, Flip-flop F input equations (22b) O 2oz=F (22c) 1 2oa=1, (23a) T 203=F Flip-flop F input equations (23b) O 203=1, (23c) 1 2o4=F (24a) T z04=F Flip-fiop F input equations (24b) O 204=F (24c) 1 2os=1, (25a) T 2o5=F Flip flop F input equations (25b) 0F205= 1, (250) 1 2oa=F (26a) T 2oo= G 01, Flip-flop F input equations (26b) 207,

1r201=F (27a) TF2: 201, ip fl p F input equations (27b) 201 1 201 z02 20s 20i 205,} Gate equation (28) r= 207, (29) Xrq= F206. Output equations (30) The preceding equations are implemented in the logic diagram shown in FIG. 2.

Waveforms relating to the reference-carrier generator 2 appear in FIG. 4. The clock signals C at g and C at h are shown idealized as impulse trains. Lapses in the time scale are shown by jagged discontinuities; a particular signal may or may not vary during such a time lapse. The time scale has been selected so that The number C represented by the states of the flipfiops in the reference-carrier generator 2 is shown as defined in Relation 18. In the period shown, C is initially 0 and increases one increment in response to each C pulse until C =l27 C then returns to 0 in response to the next C pulse and the counting cycle repeats.

Waveforms are shown (j thru n) which represent the states of all flip-flops (F thru P in the input counter of the reference-carrier generator. The states of these flip-flops represent the binary coefficients a mgkg l) of the number C in accordance with Relation 19a.

Whenever C,=a a 11ll1, where a and [1 have the values 0 or 1 in any combination, the corresponding decimal value of C will be 31, 63, 95, or 127. The C pulse at the end of a clock period during which C has any of these values will be emitted by the gate G as shown at 0- thru 1'. If, and only if, immediately preceding such a G201 1311156 F206 F207 (or F205 F2Q7)=1 (HS at O Or q), a 1-to-0 (or O-to-l) transition of X =F will occur when the G pulse terminates (as at s or t). Similarly, if, and only if, immediately preceding a G pulse F F (or F F )=1 (as at p or r), a 1-to-0 (or O-to-l) transition of X =F will occur when the G pulse terminates (as at u or r). This action results in generation of the logical two-phase carriers X and X with the proper phase relationship at all times. The respective fundamental sinusoidal components of these two logical carriers are shown at w and x, as they emerge from the reference and quadrature band-pass amplifiers (3 and 4 in FIG.1).

In summary, the following advantages will be seen to have been achieved by the invention:

The availability of separate pulse trains for triggering flip-flops and for interrogation and presetting of flip-flop states which results in substantially greater versatility of the logical design.

The reliable settling of all flip-flops to new states before interrogation and more reliable override presetting of flip-flops independent of the succeeding clock pulse, which results in the elimination of extraneous interrogation-signal spikes which in turn lead to unreliable operation and the necessity of introducing intentional delays to remove such spikes.

The reliable operation under variation of operating environment and aging which may affect the output wave form of the master oscillator.

The reduction of uncertainty in measurement of the phase displacement between the reference carrier square wave and a phase shifted carrier sine or square wave from the output transducer of an associated control system.

The frequency drift due to varying environment or aging does not produce the phase errors which result when phase shift is produced by the conventional method of resistance-capacitance networks.

The elimination of gating irregularities at the output which results in a purer fundamental wave form after filtering, and also provides greater measurement accuracy in the associated system.

The method of obtaining the two-phase square waves with the elimination of all except momentary improper phasing and of the necessity for presetting fiip-iops to obtain proper phasing.

The additional method of having all logical transitions synchronized by the master oscillator directly which results in greater reliability of operation.

While in order to comply with the statute the invention has been described in language more or less specific as to structural features, it is to be understood that the invention is not limited to the specific features shown, but that the means and construction herein disclosed comprise a preferred form of putting the invention into effect, and the invention is therefore claimed in any of its forms or modifications within the legitimate and valid scope of the appended claims.

What is claimed is:

1. A digital reference source combining in combination:

a clock means for generating a periodic pulse train;

a carrier generator for generating first and second square waves separated in phase a fixed predetermined amount from each other and having a frequency dependent upon said periodic pulse train, the periods of said first and second square waves being of equal duration, said generator comprising, a high speed counter for counting said pulse train and for supplying a signal indicative of said counted pulses, gate means for producing a trigger pulse each time said supplied signal and said pulse train assume a predetermined state, a pair of flip-flops each connected to receive as inputs said trigger pulse and to provide an output when in one state, said flip-flops connected so that each supplies the enable inputs for the other, whereby consecutive trigger pulses change the state of alternate flip-flops.

2. A digital reference source combining in combination:

clock means for generating a periodic pulse train;

a carrier generator for generating two square waves each having equal periods and a frequency dependent upon said pulse train, said generator comprising, a high speed doublet counter for counting said pulse train and for supplying a signal indicative of said counted pulses, gate means for producing an output trigger pulse each time said supplied signal and said pulse train assume a predetermined state, a pair of bistable means responsive to said trigger pulses, each bistable means providing an output when in one state, said pair of bistable means being connected so that alternate ones of the pair are changed in state in coincidence with consecutive trigger pulses.

3. A reference source combining in combination:

means for generating a pulse train;

a generator for generating two balanced square waves shifted in phase by and having a frequency dependent upon said pulse train, said generator comprising, a high speed doublet counter for counting said pulse train and for supplying a signal indicative of said counted pulses, means for producing an output pulse each time said supplied signal and said pulse train assume a predetermined state, a pair of bistable means each responsive to said output pulses, said pair being connected such that each supplies the enable inputs for the other, whereby each bistable means is changed in state in coincidence with alternate output pulses.

4. A source combining in combination:

means for generating a plurality of pulses forming a pulse train;

a generator for generating two square waves of equal period and shifted in phase by 90 and having a frequency dependent upon said pulse train, said generator comprising a high speed counter for counting said pulse train and for supplying a signal after counting a predetermined number of said pulses, gate means for producing an output trigger pulse upon time coincidence of said signal and one of said pulses, a pair of complimentary bistable means connected such that each supplies the enable inputs for the other, so that each means is responsive to alternate trigger pulses to produce as an output a square wave having rise and fall times coincident with pulses in said pulse train.

5. A square Wave generator comprising in combination:

a source of control pulses;

counting means for counting said pulses;

gate means for producing a trigger pulse after a predetermined number of said pulses have been counted, said trigger pulse being coincident With one of said control pulses, a complimentary pair of bistable means each responsive to alternate trigger pulses so as to shift from one stable state to another stable state in coincidence with said alternate trigger pulses, said pair thereby producing as outputs a pair of 25 balanced square waves having a frequency dependent upon said control pulses.

6. The device as claimed in claim and further comprising:

a first filter means connected to the output of one of other of said bistable means for filtering out all but the fundamental frequency of said square wave to provide a second sinusoidal wave having a fixed phase relationship with respect to said first sinusoidal wave.

7. The device as claimed in claim 5 wherein said clock means is comprised of an oscillator means for producing a first fixed frequency signal, trigger means for providing a two state signal the state of which is dependent upon the predetermined transition of said first signal, a flip-fiop connected to detect the state of said two state signal and for providing a second signal indicative of one of said states, a pulse switch for providing complementary output signals proportional to said second signal, a pair of gating meanshaving as a common input the output of said flipfiop, one of said gating means having as another input one of said complemented signals and the other of said gating means having as an input the other of said complemented signals, so that the output from said gates in a series of pulses having a frequency proportional to said oscillator frequency and displaced in phase with respect to each other by References Cited UNITED STATES PATENTS 2,755,440 7/1956 Andresen et a1. 318l71 XR 2,910,586 10/1959 Kohler 328 3,172,042 3/1965 Dawirs 328-30 XR 3,297,952 l/1967 Thylander 328*63 XR 3,307,092 2/1967 Trocchio 318--171 3,312,885 4/1967 Falk et al. 318-171 MILTON O. HIRSHFIELD, Primary Examiner. D. F. DUGGAN, Assistant Examiner. 

